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| 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 128mb ddr sdram module 200pin sodimm (16 mx64 based on 16mx 8 ddr sdram) 64bit non-ecc/parity revision 0.1 june. 2001
200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 revision history revision 0.0 (apr. 2001) 1. first release. revision 0.1 (june. 2001) 1. changed module current speificaton 2. changed typo size on module pcb in package dimesions. (from 2.6mm to 3mm). 3. changed ac parameter table. 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 general description pin description * these pins are not used in this module. pin name function a0 ~ a11 address input (multiplexed) ba0 ~ ba1 bank select address dq0 ~ dq63 data input/output dqs0 ~ dqs7 data strobe input/output ck0~ ck2, ck0 ~ ck2 clock input cke0 clock enable input cs0 chip select input ras row address strobe cas column address strobe we write enable dm0 ~ dm7 data - in mask vdd power supply (2.5v) vddq power supply for dqs(2.5v) vss ground vref power supply for reference v ddspd serial eeprom power supply ( 2.3v to 3.6v ) sda serial data i/o scl serial clock sa0 ~ 2 address in eeprom vddid vdd identification flag nc no connection samsung electronics co., ltd. reserves the right to change products and specifications without notice. M470L1713CT0 200pin ddr sdram sodimm 16mx64 200pin ddr sdram sodimm based on 16mx8 the samsung M470L1713CT0 is 16 m bit x 64 double data rate sdram high density memory modules based on first gen of 128mb ddr sdram respectively. the samsung M470L1713CT0 consists of eight cmos 16 m x 8 bit with 4banks double data rate sdrams in 66pin tsop- ii(400mil) packages mounted on a 200 pin glass-epoxy sub- strate. four 0.1uf decoupling capacitors are mounted on the printed circuit board in parallel for each ddr sdram. the M470L1713CT0 is dual in-line memory modules and intended for mounting into 200 pin edge connector sockets. synchronous design allows precise cycle control with the use of system clock. data i/o transactions are possible on both edges of dqs. range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory sys- tem applications. ? p erformance range ? power supply : vdd: 2.5v 0.2v, vddq: 2.5v 0.2v ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency 2, 2.5 (clock) ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 15.6us refresh interval(4k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1250 (mil) , double sided component part no. max freq. interface M470L1713CT0-c(l)a2 133mhz(7.5ns@cl=2) sstl_2 M470L1713CT0-c(l)b0 133mhz(7.5ns@cl=2.5) M470L1713CT0-c(l)a0 100mhz(10ns@cl=2) feature pin configurations (front side/back side) pin front pin front pin front pin back pin back pin back 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 vref vss dq0 dq1 vdd dqs0 dq2 vss dq3 dq8 vdd dq9 dqs1 vss dq10 dq11 vdd ck0 /ck0 vss dq16 dq17 vdd dqs2 dq18 vss dq19 dq24 vdd dq25 dqs3 vss dq26 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 dq27 vdd cb0 cb1 vss dqs8 cb2 vdd cb3 du vss ck2 /ck2 vdd cke1 du(a13) a12 a9 vss a7 a5 a3 a1 vdd a10/ap ba0 /we /s0 du vss dq32 dq33 vdd dqs4 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 dq34 vss dq35 dq40 vdd dq41 dqs5 vss dq42 dq43 vdd vdd vss vss dq48 dq49 vdd dqs6 dq50 vss dq51 dq56 vdd dq57 dqs7 vss dq58 dq59 vdd sda scl vddspd vddid 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 vref vss dq4 dq5 vdd dm0 dq6 vss dq7 dq12 vdd dq13 dm1 vss dq14 dq15 vdd vdd vss vss dq20 dq21 vdd dm2 dq22 vss dq23 dq28 vdd dq29 dm3 vss dq30 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 dq31 vdd cb4 cb5 vss dm8 cb6 vdd cb7 du/(reset) vss vss vdd vdd cke0 du(ba2) a11 a8 vss a6 a4 a2 a0 vdd ba1 /ras /cas /s1 du vss dq36 dq37 vdd dm4 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 dq38 vss dq39 dq44 vdd dq45 dm5 vss dq46 dq47 vdd /ck1 ck1 vss dq52 dq53 vdd dm6 dq54 vss dq55 dq60 vdd dq61 dm7 vss dq62 dq63 vdd sa0 sa1 sa2 du key key 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 s0 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs s functional block diagram a0 - a13 a0-a13: ddr sdrams d0 - d7 ba0 - ba1 ba0-ba1: ddr sdrams d0 - d7 ras ras : sdrams d0 - d7 cas cas : sdrams d0 - d7 cke0 cke: sdrams d0 - d7 we we : sdrams d0 - d7 notes: 1. dq-to-i/o wiring is shown as recom- mended but may be changed. 2. dq/dqs/dm/cke/ cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd 1 vddq. a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d7 d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddid strap: see note 4 v ddspd spd clock wiring clock input sdrams ck0/ ck0 ck1/ ck1 ck2/ ck2 4 sdrams 4 sdrams nc dm dqs0 dm0 *clock net wiring card edge dram1 dram2 r=120 w 5% ck ck dram3 dram4 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d4 dqs s dm dqs4 dm4 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs s dm dqs1 dm1 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d5 dqs s dm dqs5 dm5 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dqs s dm dqs2 dm2 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d6 dqs s dm dqs6 dm6 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqs s dm dqs3 dm3 i/0 0 i/0 1 i/0 2 i/0 3 i/0 4 i/0 5 i/0 6 i/0 7 d7 dqs s dm dqs7 dm7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 absolute maximum ratings parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3 .6 v voltage on v ddq supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 8 w short circuit current i os 50 ma permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. note : power & dc operating conditions (sstl_2 in/out) notes 1. includes 25mv margin for dc offset on v ref , and a combined total of 50mv margin for all ac noise and dc offset on v ref , bandwidth limited to 20mhz. the dram must accommodate dram current spikes on v ref and internal dram noise coupled to v ref , both of which may result in v ref noise. v ref should be de-coupled with an inductance of 3nh. 2.v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the difference between the input level on ck and the input level on ck . 4. these parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. the ac and dc input specifications are relative to a vref envelop that has been bandwidth limited to 200mhz. 5. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 6. these charactericteristics obey the sstl-2 class ii standards. recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.3 2.7 i/o supply voltage v ddq 2.3 2.7 v i/o reference voltage v ref vddq/2-50mv vddq/2+50mv v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v 2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v 4 input logic low voltage v il (dc) -0.3 v ref -0.15 v 4 input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.3 v ddq +0.6 v 3 input crossing point voltage, ck and ck inputs v ix (dc) 1.15 1.35 v 5 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9 ma 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 recommended operating conditions unless otherwise noted, t a =0 to 70 c ) typical case: vdd = 2.5v, t = 25?c worst case : vdd = 2.7v, t = 10?c conditions symbol typical worst operating current - one bank active-precharge; trc=trcmin;tck=100mhz for ddr200, 133mhz for ddr266a & ddr266b; dq,dm and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle idd0 - - operating current - one bank operation ; one bank open, bl=4, reads - refer to the following page for detailed test condition idd1 - - percharge power-down standby current; all banks idle; power - down mode; cke = 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 ddr sdram module i dd spec table * module i dd was calculated on the basis of component i dd and can be differently measured according to dq loading cap. symbol a2(ddr266@cl=2) b0(ddr266@cl=2.5) a0(ddr200@cl=2) unit notes typical worst typical worst typical worst idd0 640 680 640 680 560 600 ma idd1 800 880 800 880 720 800 ma idd2p 28 32 28 32 24 28 ma idd2f 160 200 160 200 144 176 ma idd2q 104 120 104 120 104 120 ma idd3p 240 280 240 280 240 280 ma idd3n 360 400 360 400 328 360 ma idd4r 1200 1360 1200 1360 1040 1160 ma idd4w 1240 1400 1240 1400 1040 1120 ma idd5 1440 1520 1440 1520 1200 1280 ma idd6 normal 16 16 16 16 16 16 ma low power 8 8 8 8 8 8 ma optional idd7a 2320 2640 2320 2640 2000 2080 ma < detailed test conditions for ddr sdram idd1 & idd7a > idd1 : operating current: one bank operation 1. typical case : vdd = 2.5v, t=25? c 2. worst case : vdd = 2.7v, t= 10? c 3. only one bank is accessed with trc(min), burst mode, address and control inputs on nop edge are changing once per clock cycle. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trcd = 2*tck, tras = 5*tck read : a0 n r0 n n p0 n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl=2, bl=4, trcd = 3*tck, trc = 9*tck, tras = 5*tck read : a0 n n r0 n p0 n n n a0 n - repeat the same timing with random address changing *50% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 i dd7a : operating current: four bank operation 1. typical case : vdd = 2.5v, t=25? c 2. worst case : vdd = 2.7v, t= 10? c 3. four banks are being interleaved with trc(min), burst mode, address and control inputs on nop edge are not changing. lout = 0ma 4. timing patterns - ddr200(100mhz, cl=2) : tck = 10ns, cl2, bl=4, trrd = 2*tck, trcd= 3*tck, read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 a0 r3 a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst - ddr266b(133mhz, cl=2.5) : tck = 7.5ns, cl=2.5, bl=4, trrd = 2*tck, trcd = 3*tck read with autoprecharge read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst - ddr266a (133mhz, cl=2) : tck = 7.5ns, cl2=2, bl=4, trrd = 2*tck, trcd = 3*tck read : a0 n a1 r0 a2 r1 a3 r2 n r3 a0 n a1 r0 - repeat the same timing with random address changing *100% of data changing at every burst legend : a=activate, r=read, w=write, p=precharge, n=nop ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dqs and dm signals vih(ac) vref + 0.31 v 3 input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v 3 input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 note 1. vid is the magnitude of the difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simula - tion. the ac and dc input specificatims are refation to a vref envelope that has been bandwidth limited 20mhz. 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 output load circuit (sstl_2) output z0=50 w c load =30pf v ref =0.5*v ddq r t =50 w v tt =0.5*v ddq input/output capacitance (v dd = 2 . 5 v, v ddq =2.5v, t a = 25 c , f=1mhz) parameter symbol min max unit input capacitance(a 0 ~ a 11 , ba 0 ~ ba 1 , ras , cas , we ) c in1 36 44 pf input capacitance(cke 0 ) c in2 36 44 pf input capacitance( cs 0 ) c in3 34 42 pf input capacitance( clk 0 , clk 1 ) c in4 34 38 pf data & dqs input/output capacitance(dq 0 ~dq 63 ) c out 8 9 pf input capacitance(dm 0 ~dm 8 ) c in5 8 9 pf ac operating test conditions (v dd = 2 . 5 v, v ddq =2.5v, t a = 0 to 70 c ) parameter value unit note input reference voltage for clock 0.5 * v ddq v input signal maximum peak swing 1.5 v input levels(v ih /v il ) v ref +0.3 1 /v ref -0.3 1 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see load circuit 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 ac timming parameters & specifications (these ac charicteristics were tested on the component) parameter symbol -tca2(ddr266a) -tcb0(ddr266b) -tca0 (ddr200) unit note min max min max min max row cycle time trc 65 65 70 ns refresh row cycle time trfc 75 75 80 ns row active time tras 45 120k 45 120k 48 120k ns ras to cas delay trcd 20 20 20 ns row precharge time trp 20 20 20 ns row active to row active delay trrd 15 15 15 ns write recovery time twr 2 2 2 tck last data in to read command tcdlr 1 1 1 tck col. address to col. address delay tccd 1 1 1 tck clock cycle time cl=2.0 tck 7.5 12 10 12 10 12 ns 5 cl=2.5 7.5 12 7.5 12 12 ns 5 clock high level width tch 0.45 0.55 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ ck tdqsck -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns output data access time from ck/ ck tac -0.75 +0.75 -0.75 +0.75 -0.8 +0.8 ns data strobe edge to ouput data edge tdqsq - +0.5 - +0.5 - +0.6 ns 5 read preamble trpre 0.9 1.1 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.75 1.25 0.75 1.25 0.75 1.25 tck dqs-in setup time twpres 0 0 0 ns 2 dqs-in hold time twpreh 0.25 0.25 0.25 tck dqs falling edge to ck rising-setup time tdss 0.2 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 0.35 tck dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 0.9 1.1 tck address and control input setup time tis 0.9 0.9 1.1 ns 6 address and control input hold time tih 0.9 0.9 1.1 ns 6 data-out high impedence time from ck/ ck thz tacmin - 400ps tacmax - 400ps tacmin - 400ps tacmax - 400ps tacmin - 400ps tacmax - 400ps ps data-out low impedence time from ck/ ck tlz tacmin - 400ps tacmax - 400ps tacmin - 400ps tacmax - 400ps tacmin - 400ps tacmax - 400ps ps input slew rate(for input only pins) tsl(i) 0.5 0.5 0.5 v/ns 6 input slew rate(for i/o pins) tsl(io) 0.5 0.5 0.5 v/ns 7 output slew rate(x4,x8) tsl(o) 1.0 4.5 1.0 4.5 1.0 4.5 v/ns 10 output slew rate(x16) tsl (o) 0.7 5 0.7 5 0.7 5 v/ns 10 output slew rate matching ratio(rise to fall) t slmr 0.67 1.5 0.67 1.5 0.67 1.5 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 note : 1. maximum burst refresh of 8 2. the specific requirement is that dqs be valid(high or low) on or before this ck edge. the case shown(dqs going f rom high_z to logic low) applies when no writes were previously in progress on the bus. if a previous write was in progress, dqs could be high at this time, depending on tdqss. 3. the maximum limit for this parameter is not a device limit. the device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. a write command can be applied with t rcd satisfied after this command. 5. for registered dinns, t cl and t ch are 3 45% of the period including both the half period jitter (t jit(hp) ) of the pll and the half period jitter due to crosstalk (t jit (crosstalk) ) on the dimm. parameter symbol -tca2(ddr266a) -tcb0(ddr266b) -tca0 (ddr200) unit note min max min max min max mode register set cycle time tmrd 15 15 16 ns dq & dm setup time to dqs tds 0.5 0.5 0.6 ns 7,8,9 dq & dm hold time to dqs tdh 0.5 0.5 0.6 ns 7,8,9 dq & dm input pulse width tdipw 1.75 1.75 2 ns power down exit time tpdex 10 10 10 ns exit self refresh to write command txsw 95 116 ns exit self refresh to bank active command txsa 75 75 80 ns 4 exit self refresh to read command txsr 200 200 200 cycle refresh interval time 64mb, 128mb tref 15.6 15.6 15.6 us 1 256mb 7.8 7.8 7.8 us 1 output dqs valid window tqh thpmin -tqhs - thpmin -tqhs - thpmin -tqhs - ns 5 clock half period thp tclmin or tchmin - tclmin or tchmin - tclmin or tchmin - ns data hold skew factor tqhs 0.75 0.75 0.8 ns dqs write postamble time twpst 0.25 0.25 0.25 tck 3 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 6. input setup/hold slew rate derating this derating table is used to increase t is /t ih in the case where the input slew rate is below 0.5v/ns. input setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 7. i/o setup/hold slew rate derating this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 0.5v/ns. i/o setup/hold slew rate based on the lesser of ac-ac slew rate and dc-dc slew rate. 8. i/o setup/hold plateau derating this derating table is used to increase tds/tdh in the case where the input level is flat below vref 310mv for a duration of up to 2ns. 9. i/o delta rise/fall rate(1/slew-rate) derating this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 5v/ns and slew rate 2 =.4v/ns then the delta rise/fall rate =-0/5ns/v. input s/h slew rate based on larger of ac-ac delta rise/fall rate and dc-dc delta rise/fall rate. 10. this parameter is fir system simulation purpose. it is guranteed by design. input setup/hold slew rate d tis d tih (v/ns) (ps) (ps) 0.5 0 0 0.4 +50 +50 0.3 +100 +100 i/o setup/hold slew rate d tds d tdh (v/ns) (ps) (ps) 0.5 0 0 0.4 +75 +75 0.3 +150 +150 i/o input level d tds d tdh (mv) (ps) (ps) 280 +50 +50 delta rise/fall rate d tds d tdh (ns/v) (ps) (ps) 0 0 0 0.25 +50 +50 0.5 +100 +100 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba 0,1 a 10 /ap a 11 a 9 ~ a 0 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h l l l h x 3 self refresh entry l 3 exit l h l h h h x 3 h x x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable h x l h l h v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4 write & column address auto precharge disable h x l h l l v l column address (a 0 ~a 8 ) 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection h x l l h l v l x all banks x h 5 active power down entry h l h x x x x l v v v exit l h x x x x precharge power down mode entry h l h x x x x l h h h exit l h h x x x l v v v dm h x x 8 no op eration (nop) : not defined h x h x x x x 9 l h h h 9 note : 1. op code : operand code. a 0 ~ a 11 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functions are same as the cbr refresh of dram. the automatical precharge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row active and precharge, bank a is selected. if both ba 0 is "high" and ba 1 is "low" at read, write, row active and precharge, bank b is selected. if both ba 0 is "low" and ba 1 is "high" at read, write, row active and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row active and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency is 0). 9. this combination is not defined for any function, which means "no operation(nop)" in ddr sdram. 200pin ddr sdram sodimm M470L1713CT0 rev. 0.1 june. 2001 tolerances : .006(.15) unless otherwise specified the used device is 16mx8 sdram, tsop sdram part no. : k4h280838c-tc/l package dimensions 2.70 2.50 units : inches (millimeters) full r 2x 0.17 (4.20) 0.456 11.40 1.896 (47.40) 0 . 2 4 ( 6 . 0 ) 0.086 0 . 7 9 ( 2 0 . 0 0 ) 2.15 (63.60) (67.60) detail z 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1) 2- f 0.07 (1.80) 1 . 2 5 ( 3 1 . 7 5 ) 0.16 0.039 (4.00 0.10) 0.096 (2.40) 0.07 (1.8) 0.150 max 0.04 0.0039 (1.00 0.10) 0 . 1 5 7 m i n ( 4 . 0 0 m i n ) (3.80 max) 0 . 1 5 7 m i n ( 4 . 0 0 m i n ) 1 0.024 typ 0.018 0.001 0.01 (0.25) (0.45 0.03 ) (0.60 typ ) 0 . 1 0 2 m i n ( 2 . 5 5 m i n ) detail y 2 0.098 2.45 40 42 39 41 z y 199 200 |
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